`timescale 1ns / 1ps
/******************************************************************************
*                                                                             *
* UTICA softcore v0.1                                                         *
*                                                                             *
* Copyright (c) 2012 Andrew D. Zonenberg                                      *
* All rights reserved.                                                        *
*                                                                             *
* Redistribution and use in source and binary forms, with or without modifi-  *
* cation, are permitted provided that the following conditions are met:       *
*                                                                             *
*    * Redistributions of source code must retain the above copyright notice  *
*      this list of conditions and the following disclaimer.                  *
*                                                                             *
*    * Redistributions in binary form must reproduce the above copyright      *
*      notice, this list of conditions and the following disclaimer in the    *
*      documentation and/or other materials provided with the distribution.   *
*                                                                             *
*    * Neither the name of the author nor the names of any contributors may be*
*      used to endorse or promote products derived from this software without *
*      specific prior written permission.                                     *
*                                                                             *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED *
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF        *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN     *
* NO EVENT SHALL THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT,         *
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT    *
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,   *
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY       *
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT         *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF    *
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.           *
*                                                                             *
******************************************************************************/
module testTopLevel;

	// Inputs
	reg clk = 0;
	reg uart_rx = 1;
	reg ready = 0;

	// Outputs
	wire [7:0] leds;
	wire uart_tx;
	wire spi_sck;
	wire spi_cs_n;
	
	// Bidirs
	wire [3:0] spi_data;

	// Instantiate the Unit Under Test (UUT)
	TopLevel uut (
		.clk_20mhz(clk), 
		.leds(leds),
		.uart_rx(uart_rx),
		.uart_tx(uart_tx),
		.spi_sck(spi_sck), 
		.spi_cs_n(spi_cs_n), 
		.spi_data(spi_data)
	);
	
	//The SPI flash
	s25fl008k #(
		.UserPreload(1),
		.mem_file_name("/home/azonenberg/native/programming/achd-soc/trunk/testprogs/13_mm/mm.mem"),
		.screg_file_name("none"),
		.unique_id(64'hdeadbeefbaadc0de)
	) flash (
		.SI(spi_data[0]), 
		.SO(spi_data[1]),
		.SCK(spi_sck),
		.CSNeg(spi_cs_n), 
		.HOLDNeg(spi_data[2]), 
		.WPNeg(spi_data[3])
		);
	
	initial begin
		#100;
		ready = 1;
		
		#100;
		//UARTSend("A");
	end
	
	always begin
		#25;
		clk = 0;
		#25;
		clk = ready;
	end
	
	task UARTSend();
		input reg[7:0] msg;
		begin
			uart_rx = 0;			//Start bit
			#8680;
			uart_rx = msg[0];	//LSB
			#8680;
			uart_rx = msg[1];
			#8680;
			uart_rx = msg[2];
			#8680;
			uart_rx = msg[3];
			#8680;
			uart_rx = msg[4];
			#8680;
			uart_rx = msg[5];
			#8680;
			uart_rx = msg[6];
			#8680;
			uart_rx = msg[7];	//MSB
			#8680;
			uart_rx = 1;			//Stop bit
			#8680;
		end
	endtask
      
endmodule

